1. Field of the Invention
This invention relates to integrated circuits and processes, and in particular to high density integrated circuits such as silicon-on-sapphire integrated circuits.
2. Description of the Prior Art
In the prior art integrated circuits have been made by treating the upper surface of a semiconductor wafer or a semiconductor layer on an insulating substrate to form impurity regions within the semiconductor material. The upper surface of the semiconductor material is usually oxidized to form a layer of thermal oxide which is then etched to form windows exposing the silicon material below. Impurities are driven into the semiconductor material through the window such as by diffusion or ion implantation. Each metal oxide semiconductor (MOS) transistor requires a drain and source which are formed through the top surface of the semiconductor. The windows formed in the insulation layer are limited in size by the resolution and alignment of the photomasking techniques. Additional surface area is consumed by the lateral diffusion of impurities if thermal diffusion is used. Ohmic contacts are normally made to selected regions by etching windows in the insulation layer, which is normally reformed by oxidation after every diffusion step and depositing aluminum or polysilicon over the insulation and exposed semiconductor material. The aluminum or polysilicon material is then etched to form an appropriate interconnection pattern. The wafer is scribed between individual integrated circuits and flexed to mechanically separate the integrated circuits from one another.
Integrated circuits which utilize a layer of semiconductor material over an insulating substrate such as sapphire are normally processed in a similar manner as a bulk silicon integrated circuit after semiconductor regions or islands have been formed to isolate the regions from one another. The semiconductor regions are normally formed by etching the semiconductor material through to the insulating substrate. For example, with silicon-on-sapphire wafers, the silicon grown on the sapphire is oriented with the &lt;100&gt; crystalline orientation pointed up and orthogonal to the upper surface of a semiconductor layer. During etching, the exposed sides or edges of the islands, which may for example be rectangular, are normally in the &lt;111&gt; which is well known in the art. The edges, for example, may have a light slope extending outward from the upper surface to the lower surface of the semiconductor material. The upper surface of the semiconductor material may be protected from etching by a mask of thermal oxide with a layer of silicon nitride deposited thereover. Individual devices such as n and p-type transistors have been made by forming windows in thermal oxide on the upper surface of a semiconductor material and diffusing or ion implanting impurities through the upper surface to form regions within the semiconductor islands.
An integrated circuit composed of a number of islands of semiconductor material have the advantage that the material of each island is isolated from the others by the insulating substrate and air, reducing isolation capacitance and permitting various voltages and n and p-type field effect transistors on respective islands.
One example of n and p channel transistors each formed on a respective silicon island is described in U.S. Pat. No. 4,183,134 issuing on Jan. 15, 1980 to Harry G. Oehler et al. entitled "High Yield Processing for Silicon-On-Sapphire CMOS Integrated Circuits" and assigned to the assignee herein. In U.S. Pat. No. 4,183,134 the device is planarized by growing a silicon dioxide layer between silicon islands such that the surface of the silicon dioxide layer is at approximately the same height above the sapphire substrate as the silicon islands. By planarizing the device that edges or sides of the silicon island were covered with silicon dioxide and are no longer exposed. The planar surface between the silicon islands and the silicon dioxide in between facilitated metallization patterns which did not have to traverse the edges or sides and corners of the silicon islands going from one island to another.
Another example of a silicon-on-sapphire integrated circuit is described in U.S. Pat. No. 3,889,287 issuing on June 10, 1979 to Michael W. Powell entitled "MNOS Memory Matrix". In U.S. Pat. No. 3,889,287 a matrix or an array of metal nitride oxide silicon (MNOS) field effect transistors are formed and interconnected from a silicon layer on sapphire which has been etched to form a number of ladder structures arranged side by side. The thickness of the semiconductor layer is approximately one micrometer. The memory transistors are formed on the rungs of the ladder with a gate electrode of polysilicon 5 micrometers wide passing over top the side rails and rungs of the ladders forming a row while the side rails of the ladder structure form a column to connect the drains and sources respectively. A diffusion is made into the side rails which are exposed which passes underneath the polysilicon gate electrode at the side rail to form a continuous path down the side rail and impurities diffused towards the memory transistor at the rung of the ladder structure to form the drain and source regions of the memory transistor. The polysilicon gate row is isolated from the ladder structures by a layer of silicon oxide and silicon nitride grown over the semiconductor material.
It is therefore desirable to provide high density transistor device structures which utilize the edges of silicon islands.
It is further desirable to diffuse impurities into the edges of semiconductor islands to form source and drain regions and to provide interconnection paths.
It is further desirable to form an MOS transistor along the edge of a silicon island.
It is further desirable to use strips or bars of silicon 4 micrometers wide to make MOS transistors across the bar and along the edge.
It is further desirable to utilize aluminum metallization for contacts which may form ohmic contacts with p regions and Schottky barrier diodes when in contact with adjacent n regions.
It is further desirable to use a new MOS transistor structure in a high density read only memory array.
It is further desirable to use a new transistor device structure to make a high voltage transistor.
It is further desirable to use a new metal nitride oxide semiconductor (MNOS) variable threshold transistor structure in a high density memory array.
It is further desirable to use a new structure for making crossovers for interconnection patterns.
It is further desirable to use a new transistor device structure to form row decoders for use in read only memories and random access memories.
It is further desirable to utilize new transistor structures to form high density circuit transmission switches.
It is further desirable to utilize a fabrication process which requires five masks.
It is further desirable to utilize a fabrication process which, even though it is high density, makes alignment of contacts to the drain and source regions non-critical.